Electrostatic discharge (ESD) is a problem in the utilization, manufacturing and/or design of the semiconductor devices. The integrated circuits manufactured on the semiconductor device can be damaged when ESD events are received from other circuits coupled to the semiconductor device or from people and/or machinery and tools touching the semiconductor device. During an ESD event the integrated circuit may receive a charge which leads to relatively large currents during a relatively short period of time. As the result of the large current (until several amps during tens of nanoseconds), the voltage inside the IC increases. If the resulting voltage, current, power or energy exceed a maximum capability of the circuits then it may create irreparable damage to the integrated circuit.
Today most integrated circuits comprise ESD protection circuitries that are able to conduct the charge of an ESD event to, for example, the ground without causing irreparable damage to the integrated circuit. Such ESD protection circuits are typically arranged near the I/O pads of the semiconductor device and are configured to conduct the charge of the ESD event directly to the ground before the current may reach the vulnerable portions of the integrated circuit.
In published article “New High Voltage ESD Protection Devices Based on Bipolar Transistors for Automotive Applications”, Gendron A. et al, 33th Electrical Overstress/Electrostatic Discharge Symposium, 11-16 Sep. 2011, a cross-sectional view of the structure of an ESD protection device as presented in FIG. 1a and FIG. 2a are usable ESD protection devices for automotive applications. If the I/O pad of the semiconductor device 100 receives an ESD event of a positive voltage, the semiconductor device forms the indicated circuit of transistors T1 and T2 as presented in FIG. 1a and FIG. 1b. The circuit of transistors T1 and T2 form a thyristor-like circuit, also often indicated with the term Silicon Controlled Rectifier (SCR). As soon as the voltage across the reverse biased N-P junction from the central N-doped region towards the P-doped region 102 becomes higher than the breakdown voltage of this junction, an avalanche phenomenon by impact ionization is created. A hole current flows through from the p-doped region 102. The p-doped region is resistive and once the voltage difference between the N-doped region (which is connected to ground) and the p-doped region 102 becomes larger than 0.3 volt, transistor T2 starts to operate, and, thus, the presented SCR starts to conduct a current from the I/O pad towards the negative or ground voltage. Thus, the breakdown voltage of the discussed junction is the trigger voltage of the ESD protection device. The start of the operation of the SCR causes the reduction of the voltage across the ESD protection device. This reduction of the voltage is termed ‘the snapback behaviour’ of the ESD protection device. If, subsequently, the current through the ESD protection device increases, the voltage across the ESD protection device also increases until the failure of the structure. In FIG. 1c the typical behaviour of such an ESD protection device is presented. As shown in FIG. 1c, if the voltage of the ESD event raises to the trigger voltage Vt the operation of the SCR starts and the voltage drops towards the holding voltage Vh. The difference between the trigger voltage Vt and the holding voltage Vh is called the snapback voltage Vsb. Subsequently, the ESD protection device is capable of conducting larger currents until the ESD protection device is damages at point 162.
As shown in FIG. 1b, in several prior art ESD protection devices, a diode D1 is arranged in parallel to the SCR. The aim of the diode is to provide a protection to negative ESD stress between IO and Neg, and that diverting the current since −0.3V that corresponds to the threshold voltage of a forward biased diode. The diode does not clamp voltage during positive stress between IO and NEG as its breakdown voltage is generally higher than the triggering voltage of the SCR to which the diode is arranged in parallel. This diode is not drawn in the cross-sectional view of the structure of FIG. 1a. Thus, if such a diode D1 is arranged in parallel, the ESD protection device becomes significantly larger.
In FIG. 2a and FIG. 2b the situation is drawn in case a negative ESD event, which is an ESD event of a negative voltage, is received by the ESD protection device which is implemented in the presented structure 100 of FIG. 2a. Another SCR, which is present in the structure, starts to operate once the voltage difference across the n-p junction from the NBL to the p-doped region 202 reaches the breakdown voltage of that junction. The operation of the ESD protection device, in case of the reception of a negative ESD event, is similar to the operation of the ESD protection device in case of the reception of a positive ESD event, with the minor difference that the current generated by the ESD event is principally conducted towards the substrate, and, consequently, to the voltage supply line which is connected to the substrate.
It is further to be noted that is certain prior art embodiments two SCR's are coupled in series, which means that the structure of FIG. 1a is manufactured twice in each other's neighbourhood and that they are electrically connected to each other via an electrical connection through one of the patterned metal layers manufactured on top of the presented structure to obtain the series arrangement.